Signal transmission speed between components and elements may improve system performance in addition to improving the performance of the individual components. For example, the signal transmission rate between a memory like a static random access memory (SRAM) or a dynamic random access memory (DRAM) and a processor may improve the performance of a computer used as a server. Owing to performance improvement of other information processing apparatuses than servers, such as communication infrastructure apparatuses, it is necessary to increase data rates of signal transmission and reception inside and outside an apparatus.
The data rate of each input/output (I/O) circuit for inputting and/or outputting signals to a range from a few Gb/s to a few tens of Gb/s may increase in many integrated circuits (ICs).
An I/O circuit may perform various signal processing operations including an operation for compensating for waveform distortion of a received signal and an operation for restoring a clock needed for receiving the signal. A circuit for performing such signal processing operations may include an analog circuit. Related art discussed in “A 90 nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10 Gb/s”, ISSCC Dig. of Tech. Papers, pp. 232-233, 609, February 2008, by O. Agazzi, et al. and “A 12.5 Gb/s SerDes in 65 nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery”, ISSCC Dig. of Tech. Papers, pp. 436-437, 613, February 2007, by M. Harwood, et al., for instance.